module muxextreg (A, B, SEL, Y);

input [7:0] A, B;
input SEL;
output [7:0] Y;

wire [7:0] A, B;
wire SEL;
reg [7:0] Y;

always @ (A or B or SEL)
begin
	if (SEL == 1'b0)
	begin
		Y = A;
	end
	else
	begin
		Y = B;
	end
end

endmodule